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M65KA512AB
512Mbit (4 Banks x 8M x 16), 133 MHz Clock Rate, Bare Die, 1.8 V Supply, Low Power SDRAM
Features
512 Mbit Synchronous Dynamic Ram - Organized as 4 Banks of 8 Mwords, each 16 bits wide Supply voltage - VDD = 1.7 to 1.9 V (1.8 V typical in accordance with JEDEC standard) - VDDQ = 1.7 to 1.9 V for Input/Output Synchronous Burst Read and Write - Fixed Burst Lengths: 1, 2, 4, 8 words or Full Page - Burst Types: Sequential and Interleaved. - Clock Frequency: 133 MHz (7.5 ns speed class) - Clock Valid to Output Delay (CAS Latency): 3 at 133 MHz - Burst Control by Burst Terminate and Precharge Command Automatic and controlled Precharge Byte control by LDQM and UDQM Low-power features: - Partial Array Self Refresh (PASR), - Automatic Temperature Compensated Self Refresh (TCSR) - Driver Strength (DS) - Deep Power-Down Mode Auto Refresh and Self Refresh LVCMOS Interface compatible with multiplexed addressing Operating temperature range - - 30to 85 C
Wafer

M65KA512AB is only available as part of a multiple memory product
March 2007
Rev 3
1/55
www.st.com 1
Contents
M65KA512AB
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Address Inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lower/Upper Data Input/Output Mask (LDQM, UDQM) . . . . . . . . . . . . . . 10 VDD Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 4.2 4.3 4.4 Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Extended Mode Register Set command . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Bank (Row) Activate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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M65KA512AB
Contents
4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14
Read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto Precharge command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Burst Terminate command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Data Mask command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Auto Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Self Refresh command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Deep Power-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5
Register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1 5.2 5.3 5.4 5.5 Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Length bits (MR0 to MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Burst Type bit (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CAS Latency bits (MR4 to MR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Extended Mode Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.5.1 5.5.2 5.5.3 Partial Array Self Refresh bits (EMR0-EMR2) . . . . . . . . . . . . . . . . . . . . 22 Driver Strength bit (EMR5-EMR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Automatic Temperature Compensated Self Refresh bits (EMR3-EMR4) . 22
6 7 8 9
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
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List of tables
M65KA512AB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Extended mode Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 DC characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Self-Refresh current values in Normal Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AC characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
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M65KA512AB
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Chip Enable Signal during Read, Write and Precharge ac waveforms. . . . . . . . . . . . . . . . 30 Read with Precharge ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Read with Auto Precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Suspend during Burst Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Random Column Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Random Row Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Column Interleaved Read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Burst Column Read followed by Auto Precharge ac waveforms . . . . . . . . . . . . . . . . . . . . 37 Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Byte Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Mode Register Set ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Clock Suspend during Burst Write ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Random Column Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Random Row Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Column Interleaved Write ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Burst Column Write followed by Auto Precharge ac waveforms. . . . . . . . . . . . . . . . . . . . . 45 Precharge termination ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power-On sequence ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Power-Down mode and Clock Masking ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Auto refresh ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Self refresh ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Deep Power-Down Entry ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Deep Power-Down Exit ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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Description
M65KA512AB
1
Description
The M65KA512AB is a 512 Mbit Low Power Synchronous DRAM (SDRAM). The memory array is organized as 4 Banks of 8,388,608 words of 16 bits each. The LPSDRAM achieves low power consumption and high-speed data transfer using the pipeline architecture. The device architecture is illustrated in Figure 2: Functional block diagram. It uses Burst mode to read and write data. It is capable of one, two, four, eight-word and full-page, sequential and interleaved Burst. To minimize current consumption during self-refresh operations, the M65KA512AB includes three mechanisms configured via the Extended Mode Register:
Automatic Temperature Compensated Self Refresh (ATCSR) used to adapt the refresh time according to the operating temperature (see Table 5: Extended mode Register definition) Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM memory array. This area can be configured to half bank, a quarter of bank, one bank, two banks or all banks. This mechanism allows to reduce the device Standby current by refreshing only the part of the memory array that contains essential data. The Deep Power-Down (DPD) mode completely halts the refresh operation and achieves minimum current consumption by cutting off the supply voltage from the whole memory array.
The device is programmable through two registers, the Mode Register and the Extended Mode Register:
The Mode Register is used to select the CAS Latency, the Burst Type (sequential, interleaved) and the Burst Length (1-, 2-, 4-, 8-word width or full page) through programming the A6 to A4 bits, the A3 bit and the A2 to A0 bits, respectively (see Table 4). The Extended Mode Register is used to program the low-power features (PASR, ATCSR) and Driver Strength) to reduce the current consumption during the Self Refresh operations. For more details, refer to Table 5: Extended mode Register definition, and to Section 4.2: Extended Mode Register Set command.
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M65KA512AB Figure 1. Logic diagram
VDD VDDQ
Description
13 A0-A12 2 BA0-BA1 E RAS CAS K KE W M65KA512AB LDQM UDQM 16 DQ0-DQ15
VSS
VSSQ
AI12117
Table 1.
Signal names
Name A0-A12 BA0-BA1 DQ0-DQ15 K KE E W RAS CAS UDQM LDQM VDD VDDQ VSS VSSQ Address Inputs Bank Select Inputs Data Inputs/Outputs Clock Input Clock Enable Input Chip Enable Input Write Enable Input Row Address Strobe Input Column Address Strobe Input Upper Data Input/Output Mask Lower Data Input/Output Mask Supply voltage Input/Output Supply voltage Ground Input/Output Ground Description Direction Inputs Inputs Input/Outputs Input Input Input Input Input Input Input Input Supply Supply -
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Description Figure 2. Functional block diagram
TCSR, PASR Extended Mode Register Self Refresh Logic & Timer Internal Row Counter Row Active State Machine Row PreDecoders 8 Mb x 16 Bank 3 8 Mb x 16 Bank 2 8 Mb x 16 Bank 1 Sense AMP & I/O Gate 8 Mb x 16 Bank 0 Memory Cell Array Column Decoders Bank Select A0 A1 Address Buffers ... A12 BA1 BA0 ... Address Registers Burst Counter Burst Length Column Add Counter ... Row Decoders Row Decoders Row Decoders
M65KA512AB
K KE E RAS CAS W U/LDQM
Refresh Column Active
I/O Buffer & Logic
DQ0 ...
Row Decoders
...
Column PreDecoders
DQ15
Mode Register
CAS Latency
Data Out Control
ai12118
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M65KA512AB
Signal descriptions
2
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals connected to this device.
2.1
Address Inputs (A0-A12)
The A0-A12 Address Inputs are used to select the row or column to be made active. If a row is selected, all thirteen A0-A12 Address Inputs are used. If a column is selected, only the ten least significant Address Inputs, A0-A9, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2
Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Banks Select Address Inputs are used to select the bank to be made active. The device must be enabled, the Row Address Strobe, RAS, must be Low, VIL, the Column Address Strobe, CAS, and W must be High, VIH, when selecting the addresses. The address inputs are latched on the rising edge of the clock signal, K.
2.3
Data Inputs/Outputs (DQ0-DQ15)
The Data Inputs/Outputs output the data stored at the selected address during a Read operation, or are used to input the data during a write operation.
2.4
Chip Enable (E)
The Chip Enable input E activates the memory state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.5
Column Address Strobe (CAS)
The Column Address Strobe, CAS, is used in conjunction with Address Inputs A0-A9 and BA1-BA0, to select the starting column location prior to a Read or Write.
2.6
Row Address Strobe (RAS)
The Row Address Strobe, RAS, is used in conjunction with Address Inputs A0-A12 and BA1-BA0, to select the starting address location prior to a Read or Write.
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Signal descriptions
M65KA512AB
2.7
Write Enable (W)
The Write Enable input, W, controls writing.
2.8
Clock Input (K)
The Clock signal, K, is used to clock the Read and Write cycles. During normal operation, the Clock Enable pin, KE, is High, VIH. The clock signal K can be suspended to switch the device to the Self-Refresh, Power-Down or Deep Power-Down mode by driving KE Low, VIL.
2.9
Clock Enable (KE)
The Clock Enable, KE, pin is used to control the synchronizing of the signals with Clock signal K. If KE is High, VIH, the next Clock rising edge is valid. When KE is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KE is also involved in switching the device to the Self-Refresh, Power-Down and Deep Power-Down modes.
2.10
Lower/Upper Data Input/Output Mask (LDQM, UDQM)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the Read or Write data. The DQM latency is two clock cycles for read operations and there is no latency for write operations.
2.11
VDD Supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read and Write).
2.12
VDDQ Supply voltage
VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDD. VDDQ can be tied to VDD or can use a separate supply. It is recommended to power-up and power-down VDD and VDDQ together to avoid certain conditions that would result in data corruption.
2.13
VSS Ground
Ground, VSS, is the reference for the core power supply. It must be connected to the system ground.
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M65KA512AB
Signal descriptions
2.14
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS.
Note:
Each device in a system should have VDD and VDDQ decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package).
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Operations
M65KA512AB
3
Operations
There are 7 operating modes that control the memory. Each of these is described in this section, see Table 2: Operating mode, for a summary.
3.1
Power-Up
The Low-Power SDRAM has to be powered up and initialized in a well determined manner. Power must be applied to VDD and VDDQ simultaneously and, at the same time, the clock signal must be started. After Power-Up, a minimum initial pause of 200s is required. From power-up until the Precharge command is issued, the KE and DQM signals must be held High. The Precharge command must then be issued to all banks, and 2 or more Auto Refresh cycles must be executed after the precharge is completed and the minimum tRP is satisfied. Once these cycles are completed, a Mode Register Set command must be issued to program the specific operation mode (CAS Latency, Burst Length, etc.). After issuing the Mode Register Set command, the device will not accept any other command for tRSC. After issuing the Extended Mode Register Set command the device will not accept any other command for tRSC. The device is now ready for normal operation. Refer to Figure 22 for a detailed description of the Power-Up ac waveforms.
3.2
Burst Read
The Read command is used to switch the device to Burst Read mode (see Section 4.5: Read command for details). In Burst Read mode the data is output in bursts synchronized with the clock. Burst Read opertions are initiated by driving E and CAS Low, VIL, W and RAS High, and VIH, at the positive edge of the clock signal, K. Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Burst Read command is issued, the Burst Read operation is followed by an Auto Precharge cycle. If A10 is Low (set to `0'), the row will remain active for subsequent accesses. BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select the starting column location. The Burst Length, Burst Type, and CAS Latency depend on the values programmed by issuing a Mode Register Set command (see Section 5.1: Mode Register description). After a Burst Read operation is completed, data outputs become High-Z. Refer to Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11 and Figure 12 for a detailed description of Burst Read ac waveforms.
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M65KA512AB
Operations
3.3
Burst Write
The Write command is used to switch the device to Burst Write mode (see Section 4.4: Write command for details). In Burst Write mode the data is input in bursts synchronized with the clock. Burst Write operations are initiated by driving E, CAS and W Low, VIL, and RAS High, and VIH, at the positive edge of the clock signal, K. Burst Write can be accompanied by an Auto Precharge cycle depending on the state of the A10 Address Input. If A10 is High (set to `1') when the Write command is issued, the Write operation is followed by an Auto Precharge cycle. If A10 is Low (set to `0'), Auto Precharge is not selected and the row will remain active for subsequent accesses. BA1 and BA0 are used to select the bank, and the A0-A9 address inputs are used to select the starting column location. Refer to Figure 13, Figure 14, Figure 16, Figure 17, Figure 18, Figure 19 and Figure 20 for a detailed description of Burst Write ac waveforms.
3.4
Self Refresh
In Self Refresh mode, the data contained in the Low-Power SDRAM memory array is retained and refreshed. The Low-Power SDRAM refresh cycles are asynchronous. All banks must be precharged prior to executing a Self-Refresh operation. The Self-Refresh mode is entered by driving KE Low (set to `0'), with E, RAS, and CAS Low, and W High (set to `1'). When in this mode, the device is not clocked any more. The Self Refresh mode is exited by driving KE from Low to High, with E High, RAS, CAS and W Don't Care, or with E Low and RAS, CAS and W High. The Self Refresh operation is performed according to the settings of Extended Mode Register bits EMR0 to EMR2. They configure the amount of the memory to be refreshed (Partial Array Self Refresh).
3.5
Auto Refresh
The Auto Refresh mode is used to refresh the Low-Power SDRAM in normal operation mode whenever needed. All banks must be precharged prior to executing an Auto Refresh operation. During the Auto Refresh, the address bits are "Don't Care", because the specific address bits are generated by the internal refresh address counter.
3.6
Power-Down
In Power-Down mode, the current is reduced to the standby current (IDD3P). All banks must be precharged before entering Power-Down mode. For the memory to enter the Power-Down mode, KE must be held Low (set to `0'), after the Precharge Time tRP, with E High (set to `1'), RAS, CAS and W Don't Care, or with E Low, RAS, CAS and W High.
13/55
Operations
M65KA512AB
3.7
Deep Power-Down
The purpose of this mode is to achieve maximum power reduction by cutting the power supply to the whole memory array. Data is no longer retained when the device enters Deep Power-Down Mode. All banks must be precharged before entering Deep Power-Down mode. The M65KA512ABM65KA512AB enters Deep Power Down Mode by holding E and W Low with RAS and CAS High at the rising edge of the clock, K, while driving KE Low (see Figure 26: Deep Power-Down Entry ac waveforms). The M65KA512AB exits Deep Power-Down mode by asserting KE High. A special sequence is then required before the device can take any new command into account: 1. 2. 3. 4. 5. Maintain No Operation status conditions for a minimum of 200s, Issue a Precharge command to all banks of the device (see Section 4.6: Precharge command for details), Issue a Mode Register Set command to initialize the Mode Register bits, Issue an Extended Mode Register Set command to initialize the Extended Mode Register bits, Issue 2 or more Auto Refresh commands.
The Deep Power-Down mode exit sequence is illustrated in Figure 27: Deep Power-Down Exit ac waveforms. Note: The 2 Auto Refresh commands can be issued either after or before the configuration of the Mode and Extended Mode Registers.
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M65KA512AB Table 2. Operating mode(1)
KEn-1 KEn E RAS CAS W A10 A11, A12 Valid A0-A9 Start Column Address Start Column Address BA0BA1
Operations
Operating mode
UDQM/L DQM Valid
Burst Read
VIH
X
VIL
VIH
VIL
VIH
VIL
Bank Select Bank Select X X X
Burst Write Self Refresh Auto Refresh Power-Down with Precharge Deep PowerDown Device Deselect No operation
VIH VIH VIH VIH VIH VIH VIH
X VIL VIH VIL VIL X X
VIL VIL VIL VIL VIH VIL VIH VIL
VIH VIL VIL VIH X VIH X VIH
VIL VIL VIL VIH X VIH X VIH
VIL VIH VIH VIH X VIL X VIH
VIL
Valid X X X
X X X X
X X X X X
X X
X X X
1. X = Don't Care VIL or VIH.
15/55
Commands
M65KA512AB
4
Commands
There are 14 basic commands that control the memory. They can be combined to obtain 21 higher level commands shown in Table 3: Commands.
4.1
Mode Register Set command
The Mode Register Set command is issued by applying VIL to E, RAS, CAS and W and by setting BA0 and BA1 to `0'. The Mode Register Set command is used to configure the specific mode of operation of the device by programming the Mode Register:

Burst Length (1, 2, 4, 8, Full Page), CAS Latency (2, or 3), Burst Type (sequential or interleaved).
The Mode Register Set command must be executed after the Power-Up sequence prior to issuing a Bank(Row) Activate command (see Figure 15: Mode Register Set ac waveforms).
4.2
Extended Mode Register Set command
The Extended Mode Register Set command is issued by applying VIL to E, RAS, CAS and W, and then by setting BA0 to `0', and BA1 to `1'. The Extended Mode Register Set command is used to configure the self refresh operation of the device and the driver strength by programming the Extended Mode Register bits:

Partial arrays to be refreshed (all banks, two banks, one bank), Driver strength (full, 1/2 strength, 1/4 strength, 1/8 strength).
The Extended Mode Register bit controlling the Automatic TSCR (A9) should always be cleared to `0' (A9 = `1' is reserved). The Extended Mode Register Set command must be executed after the Power-Up sequence prior to issuing a Bank(Row) Activate command.
4.3
Bank (Row) Activate command
The Bank (Row) Activate command is used to activate a row in a specific bank of the device. This command is initiated by driving E and RAS Low, and CAS and W High, VIH, at the positive edge of the clock signal, K. The value on BA1 and BA0 selects the bank, and the value on A0-A12 selects the row. The selected row remains active for column access until a Precharge command is issued to that bank. A minimum time of tRCD is required after issuing the Bank (Row) Active command prior to initiating Read and Write operations from and to the activated bank.
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M65KA512AB
Commands
4.4
Write command
The Write command is used to switch the Low-Power SDRAM to Burst Write mode (see Section 3.3: Burst Write mode).
4.5
Read command
The Read command is used to switch the Low-Power SDRAM to Burst Read mode (see Section 3.2: Burst Read).
4.6
Precharge command
The Precharge command is used to close the open row in a particular bank or the open row in all banks. When the precharge command is issued with address A10 driven High, all banks will be precharged. If A10 is driven Low, the open row in a particular bank will be precharged. The bank(s) will be available when the minimum tRP time has elapsed after the precharge command has been issued.
4.7
Auto Precharge command
The Auto Precharge command is used to close the open row in a specific bank after a Read or Write operation. A10 is High, VIH, when a Read (or Write) command is issued.
4.8
Burst Terminate command
The Burst Terminate command is used to terminate a Burst operation. A Burst operation can be interrupted by using the Precharge command (see Section 4.6: Precharge command for details), or by issuing the Burst Terminate command. Issuing the Burst Terminate command during a Burst Read or Write cycle will terminate the burst while leaving the bank open.
4.9
Data Mask command
The Data Mask command is used to mask Read or Write data.A Data Mask command issued during a Read operation will disable the data outputs, switching them to the high impedance state after a delay of two clock cycles. A Data Mask command issued during a Write operation will disable the data inputs with no delay.
4.10
Clock Suspend command
The Clock Suspend command is used to interrupt the internal clock of the LPSDRAM. The command is controlled by the Clock Enable input, KE, which is kept High, VIH, in normal access mode.The Clock Suspend command is issued by driving KE Low,VIL, thus freezing the internal clock, and extending data Read and Write operations.
17/55
Commands
M65KA512AB
4.11
Auto Refresh command
The Auto Refresh command is used to put the device in Auto refresh mode (see Section 3.5: Auto Refresh and Figure 24: Auto refresh ac waveforms).
4.12
Self Refresh command
The purpose of the Self Refresh command is used to put the device in Self Refresh mode to retain and refresh the data contained in the Low-Power SDRAM memory array. In Self Refresh mode, the Low-Power SDRAM runs Refresh cycles asynchronously. The Self Refresh cycle is performed according to the Extended Mode Register bits EMR0 to EMR2 that configure the part of the memory array being refreshed (Partial Array Self Refresh). For more information on how the command is issued, refer to Figure 25: Self refresh ac waveforms.
4.13
Power-Down command
The Power-Down command is used to put the device in Power-Down mode where the operating current is reduced to the Standby current. All banks must be precharged and a minimum time of tRP must elapse before issuing the Power-Down command.
4.14
Deep Power-Down command
The Deep Power-Down command is used to switch the Low-Power SDRAM to Deep PowerDown Mode. This mode provides maximum power reduction as it cuts the power of the entire memory array of the device. For more information on how the command is issued and its exit sequence, see Section 3.7: Deep Power-Down, Figure 26: Deep Power-Down Entry ac waveforms, and Figure 27: Deep Power-Down Exit ac waveforms.
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M65KA512AB Table 3. Commands(1)
KEn-1 VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIH VIL VIH VIH VIH VIH VIL KE X X X X X X X X X VIH VIL VIH X X VIH VIL VIH E VIL VIL VIL VIL VIL VIL VIL VIL VIL VIL X X X X VIL VIL VIH VIL VIH VIL VIH VIL VIL X RAS VIL VIL VIL VIH VIH VIH VIH VIL VIL VIH X X X X VIL VIL X VIH X VIH X VIH VIH X CAS VIL VIL VIH VIL VIL VIL VIL VIH VIH VIH X X X X VIL VIL X VIH X VIH X VIH VIH X W VIL VIL VIH VIH VIH VIL VIL VIL VIL VIL X X X X VIH VIH X VIH X VIH X VIH VIL X UDQM/ LDQM X X X VIL VIL VIL VIL X X X X X VIL VIH X X X X X X X X X X X X X X X X X X X X DQ0DQ15 X X X X X X X X X X X X X High-Z X X Addr.
(2)
Commands
Command Mode Register Set Extended Mode Register Set Bank (Row) Activate Read Read with Auto Precharge Write Write with Auto Precharge Precharge all BANKS Precharge selected Bank Burst Terminate Clock Suspend Entry Clock Suspend Exit Data Mask / Output Enable Data Mask / Output Disable Auto-Refresh Self-Refresh Entry Self-Refresh Exit(5)
A10 X X
BA0BA1
(3) (4)
Row address Column Column Column Column X X X X X X X X X VIL VIH VIL VIH VIH VIL
V V V V V X V X X X X X X X X
Power-down Entry
VIH
VIL
X
Power-down Exit Deep Power-down Entry Deep Power-down Exit
VIL VIH VIL
VIH VIL VIH
X
X X
1. X = Don't Care (VIL or VIH), V = Valid Data. 2. Addresses AO to A12 except A10. 3. BA1 and BA0 must both be set to `0' to issue the Mode Register Set Command. 4. BA1 and BA0 must be set to `1' and `0', respectively, to issue the Extended Mode Register Set Command. 5. The Self-Refresh mode is exited by asynchronously driving KE from Low to High
19/55
Register descriptions
M65KA512AB
5
5.1
Register descriptions
Mode Register description
The Mode Register is used to select the CAS Latency (2 or 3), the Burst Type (sequential, interleaved), the Burst Length (1-, 2-, 4-, 8-word width or full page). It is loaded by issuing a Mode Register Set command that programs A0 to A12 address bits. The values placed on the address lines are then latched into the Mode Register. BA0-BA1 must be set to `0'. See Table 4: Mode Register Definition, for more details.
5.2
Burst Length bits (MR0 to MR2)
Bits 0 to 2 (MR0 to MR2) of the Mode Register are used to configure the Burst Length. The burst Length is the number of words that are output or input during a read or a write operation, respectively. It can be set to 1, 2, 4, 8 words or full page.
5.3
Burst Type bit (MR3)
Bit 3 (MR3) of the Mode Register is used to set the Burst Type. The Burst Type defines the order in which the address locations are accessed during a burst operation. It can be either sequential or interleaved. The type of application microprocessor must be taken into account when selecting the Burst Type: some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. Both Burst Types support burst length of 1, 2, 4 or 8 words. Full page burst is also available when the sequential burst type is selected.
5.4
CAS Latency bits (MR4 to MR6)
The CAS latency is the most critical of the Mode Register parameters. It defines the number of clocks cycles between the detection of a Read command to the first data output valid. It can be set to two or three clock cycles. The value of this parameter is determined by the frequency of the clock and the speed grade of the device. Table 4.
Address Bits A12-A7
Mode Register Definition
Mode Register bit Register description Value 0000000 010 2 clock cycles 3 clock cycles(1) Description
A6-A4
MR6-MR4
CAS Latency bits
011
Other configurations reserved
20/55
M65KA512AB Table 4.
Address Bits A3
Register descriptions Mode Register Definition
Mode Register bit MR3 Register description 0 Burst type 1 000 001 010 A2-A0 MR2-MR0 Burst Length bit 011 111 Interleaved 1 word (A3 is Don't Care) 2 words (A3 is Don't Care) 4 words (A3 is Don't Care) 8 words (A3 is Don't Care) Full Page if A3 = 0 Reserved if A3 = 1 Value Description Sequential
Other configurations reserved BA1-BA0 00
1. At 133MHz, the CAS Latency must be set to 3.
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Register descriptions
M65KA512AB
5.5
Extended Mode Register description
The Extended Mode Register is used to configure the low-power self-refresh operation of the device (PASR, DS). It is used to select the area of the memory array refreshed during Partial Array Self Refresh operations, and the driver strength. It is loaded by issuing a Extended Mode Register Set command that programs A0 to A12 address bits. The values placed on the address lines are then latched into the Extended Mode Register. BA0 and BA1 must be set to `0' and `1' respectively. See Table 5: Extended mode Register definition, for more details.
5.5.1
Partial Array Self Refresh bits (EMR0-EMR2)
Bits EMR0 to EMR2 of the Extended Mode Register allow to configure the amount of memory that will be refreshed during a Self Refresh operation (see Section 3.4: Self Refresh). It can be set to:

All Banks (banks 0, 1, 2, and 3) Two Banks (banks 0 and 1) One Bank (bank 0).
It is important to note that the data stored in the banks or portion of banks which are not refreshed, are lost. As an example, data stored in banks 1, 2 and 3 are lost when the PASR is set to one bank (bank 0 refreshed).
5.5.2
Driver Strength bit (EMR5-EMR6)
Extended Mode Register bits, EMR5 and EMR6, can be used to select the driver strength of data outputs. This value should be set according to the application requirements.
5.5.3
Automatic Temperature Compensated Self Refresh bits (EMR3-EMR4)
The M65KA512ABM65KA512ABhas a built-in temperature sensor that controls automatically the internal self refresh rate.
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M65KA512AB Table 5.
Address bits A12-A10
Register descriptions Extended mode Register definition
Mode Register bit Description Automatic Temperature Compensated Self-Refresh (ATCSR) 0000 0 1 00 00 A6-A5 EMR6-EMR5 Driver strength bits 01 10 11 A4-A3 00 000 A2-A0 EMR2-EMR0 Partial Array Self- 001 Refresh bits 010 All Banks Two Banks (BA1=0) One Bank (BA0 and BA1 =0) Full strength 1/2 strength 1/4 strength 1/8 strength Enabled Reserved Value Description
A9
EMR9
A8-A7
-
Other configurations reserved BA1-BA0 10
23/55
Maximum rating
M65KA512AB
6
Maximum rating
Stressing the device above the ratings listed in Table 6: Absolute maximum ratings, may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute maximum ratings
Value Symbol TJ TSTG VIO VDD, VDDQ IOS Parameter Min Junction temperature Storage temperature Input or Output voltage Supply voltage Short Circuit Output current - 30 - 55 - 0.5 - 0.5 50 Max 85 125 2.3 2.3 C C V V mA Unit
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M65KA512AB
DC and ac parameters
7
DC and ac parameters
This section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 7: Operating and ac measurement conditions. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 7.
Symbol VDD VDDQ TJ CL tT, tR, tF VIL VIH VREF Supply voltage Input/Output supply voltage Junction temperature Load capacitance Input Transition Time between VIL and VIH Input Rise/Fall time Input Pulses Low voltage Input Pulses High voltage Input and Output Timing ref. voltages
Operating and ac measurement conditions
Parameter(1) M65KA512AB Units Min 1.7 1.7 - 30 30 0.5 0.2 1.6 0.9 Max 1.9 1.9 85 V V C pF ns V V V
1. All voltages are referenced to VSS = 0 V.
Figure 3.
AC measurement I/O waveform
Input Timing Reference Voltage 1.6V VDDQ/2 0.2V
Output Transition Timing Reference Voltage VDDQ VDDQ/2 0V
AI08009c
25/55
DC and ac parameters Figure 4. AC measurement load circuit
M65KA512AB
Output CL
AI12109
Table 8.
Symbol
Capacitance
Parameter Signal M65KA512ABM65 KA512AB(1) Min Max 4.5 4.5 6.0 pF pF pF Unit
CI1 Input capacitance CI2 CIO Data I/O capacitance
K A0-A11, BA0, BA1, KE, E, RAS, CAS, W, UDQM, LDQM DQ0-DQ15
2.0 2.0 3.5
1. TJ = 25 C, f = 1 MHz
Table 9.
Symbol
DC characteristics 1
Parameter Test condition(1) M65KA512ABM65KA5 12AB Min Max 2 1.5 0.3 VDDQ + 0.3 0.2 A A V V V V Unit
ILI ILO VIL
(2)
Input Leakage current Output Leakage current Input Low voltage Input High voltage Output Low voltage Output High voltage
0V VIN 1.8V 0V VOUT 1.8V VIN = 0V VIN = 0V IOUT = 100A VIN = 0V
-2 - 1.5 - 0.3 0.8 VDDQ
VIH(3) VOL VOH
IOUT = -100A VIN = 0V VDDQ- 0.2
1. TJ = -30 to 85 C. 2. VIL (min.) = -0.5 V (pulse width 5 ns) 3. VIH (max.) = 2.3 V (pulse width 5 ns).
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M65KA512AB Table 10.
Symbol
DC and ac parameters
DC characteristics 2
Parameter Test condition(1) M65KA512AB Unit Max 70 mA 70 0.8 mA 0.6
IDD1(2) IDD2P IDD2PS
Operating current
CAS Latency = 2 Burst length = 1, one bank active CAS Latency = 3 tRC tRC(min), IOL = 0 mA KE VIL(max), tK = tK(min) KE VIL(max), tK = KE VIH (min), E VIH (min), tK = tK(min) Input signals changed once in 30 ns All other pins VDD - 0.2 V or 0.2 V KE VIH (min), tK = Input signals are stable
Precharge Standby current in Power-Down Mode
IDD2N
4.0 mA 2.0 3.0 mA 1.2 10 mA 7 50 mA 85 90 See Table 11 10 mA A A
Precharge Standby current in Non Power-Down Mode
IDD2NS IDD3P IDD3PS IDD3N Active Standby current in Power-Down Mode
KE VIL(max), tK = tK(min) KE VIL(max), tK = KE VIH (min), E VIH (min), tK= tK(min) Input signals changed once in 30 ns All other pins VDD - 0.2 V or 0.2 V KE VIH (min), tK = Input signals are stable
Active Standby current in Non Power-Down Mode
IDD3NS IDD4(2) IDD5 IDD6 IDD7 Burst Mode current Auto-Refresh current Self-Refresh current Standby current in Deep Power-Down Mode
CAS Latency = 2 tK tK (min), IOL = 0 mA CAS Latency = 3 All banks active tRRC tRRC (min), All banks active KE 0.2 V KE 0.2 V
1. TJ = -30 to 85 C. 2. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output open.
Table 11.
Self-Refresh current values in Normal Operating Mode
Memory array(1)
Temperature in C Typ 70 TJ 85 40 TJ 70 -30 TJ 40
4 Banks Max 800 550 300 Typ
2 Banks Max 650 380 240 Typ
1 Bank Max 490 290 210
Unit
A A A
1. VDD = 1.8 0.1 V, VDDQ = 1.8 0.1 V, VSSQ = 0 V.
27/55
DC and ac parameters Table 12.
Symbol
M65KA512AB AC characteristics 1
Alt. Parameter M65KA512AB M65KA512AB Min. CAS Latency=3 1.9 0.9 CAS Latency=3 7.5 15 2.5 2.5 1.9 1.9 0.9 1.9 0.9 1.9 0.9 2 0 CAS Latency=3 CAS Latency=2 0 0 Max. 6 8 6 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
tAC tAS(1) tAH(1) tCK tCHW tCLW tCKS(1) tCKSP(1) tCKH(1) tCS tCH tCMH(1) tDS(1) tDH(1) tOH tOLZ tOHZ tLZ tHZ tCH tCL
Access Time from clock CAS Latency=2 Address Setup Time Address Hold Time Clock Cycle Time CAS Latency=2 Clock High Pulse Width Clock Low Pulse Width Clock Enable Setup Time Clock Enable Setup Time (Power-Down Exit) Clock enable Hold Time
tCMS(1) Command Setup Time Command Hold Time Data-Input Setup Time Data-Input Hold Time Data-out Hold Time Clock to Data Output in Low-Z Time Clock to Data Output in High-Z Time
1. If tT is greater than 0.5 ns, (tT- 0.5) or ((tR + tF)/2 - 0.5) should be added.
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M65KA512AB Table 13.
Symbol
DC and ac parameters
AC characteristics 2
Alt. Parameter M65KA512ABM65KA51 2AB Min. Max. 2*tCK + 22.5 2 90 112.5 120 27.5 60 22.5 2 0.5 120000 64 30
(1)
Unit
tDPL tDAL tMRD tRC(2) tRC tRC2 tRCD tRAS tRP tRRD tREF tT tRSC
Delay Time, Write Command to Data Input Data Input Valid to Precharge Command Mode Register Set Cycle Time RAS Cycle Time (normal operation) RAS Cycle Time (refresh operation) RAS Cycle Time (Self Refresh Exit to Refresh or Bank/Row Activate Command) Delay Time, RAS Active to CAS Active RAS Active Time RAS Precharge Time Delay Time, RAS Active to RAS Bank Active Refresh Time Input Transition Time between VIL and VIH CAS Latency = 2 CAS Latency = 3
2
ns ns
(1)
ns ns ns ns ns ns
(1)
ms ns
1. The unit is the system Clock cycle time. 2. A new command can be issued tRC after the Self Refresh mode is exited.
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DC and ac parameters Figure 5.
T21
M65KA512AB Chip Enable Signal during Read, Write and Precharge ac waveforms
AI09959b
T19
T20
T17
T18
CAb
T16
T15
T14
T13
DAb2
DAb3
DAb4
T11
T12
T10
T9
T8
T7
T6
CAa
QAa1
QAa2
QAa3
QAa4 DQN
T3
T0
High
Low
1. The Chip Enable signal, E, must be issued at a minimum rate with respect to the other signals. 2. Burst Length = 4 words, Latency = 3 clock cycles. 3. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A, DAan= Data n written to Column a in Bank A.
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DQ0-DQ15
Address
LDQM/ UDQM
RAS
CAS
BA0
BA1
KE
A10
W
K
E
Hi-Z
Bank/Row Activate in Bank A
T2
Low
T1
Low
RAa
RAa
Read from Bank A
T4
T5
Write in Bank A
DAb1
Precharge Bank A
M65KA512AB Figure 6. Read with Precharge ac waveforms
T0 tCK K tCHW KE tCKS E tCS RAS tCH tCKH tCLW T1 T2 T3 T4 T5 T6 T7 T8 T9
DC and ac parameters
T10
T11
T12
T13
CAS
W
BA0
BA1
A10
Address tAS LDQM/ UDQM tAH Low
tAC DQ0-DQ15 Hi-Z
DQN DQN+1 DQN+2 DQN+3
tOHZ
tRCD tRAS
tOLZ
tOH tRP tRC
Bank/Row Activate in Bank A
Read from Bank A
Precharge in Bank A
Bank/Row Activate in Bank A
AI09934b
1. Burst Length = 4 words, Latency = 3 clock cycles.
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DC and ac parameters Figure 7. Read with Auto Precharge ac waveforms
Auto Precharge Start from Bank C T0 tCK K tCHW KE tCKS E tCS RAS tCH tCKH tCLW T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
M65KA512AB
T12
T13
CAS
W
BA0
BA1
A10
Address tAS LDQM/ UDQM Low tAH tAC Hi-Z
DQN DQN+1 DQN+2 DQN+3
tOH
DQ0-DQ15
tRCD
tOLZ tRAS, tRRD tRC
tOHZ
Bank/Row Activate in Bank C
Read with Auto Precharge from Bank C
Bank/Row Activate in Bank D
Bank/Row Activate in Bank C
AI09935b
1. Burst Length = 4 words, Latency = 3 clock cycles.
32/55
M65KA512AB
Figure 8.
T0 K
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10 T11 T12 T15 T16
T13
T14
T17
KE
E
RAS
CAS
1. Burst Length = 4 words, Latency = 3 clock cycles.
W BA0 BA1 A10 RAa Address RAa CAa LDQM/ UDQM Low DQ0-DQ15 Hi-Z QAa1 QAa2 QAa3 QAa4 Hi-Z Bank/Row Activate in Bank A Read from Bank A Clock Suspended during 1 cycle Clock Suspended during 2 cycles Clock Suspended during 3 cycles
Clock Suspend during Burst Read ac waveforms
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
End of Read
AI09949
DC and ac parameters
33/55
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DC and ac parameters
Figure 9.
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
KE
E
RAS
CAS
1. Burst Length = 4 words, Latency = 3 clock cycles.
RAa RAa RAa CAa CAb CAc RAa CAa QAa1 QAa2 QAa3 QAa4 DQN QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 Read from Bank A Read from Bank A Read from Bank A Precharge in Bank A Bank/Row Activate in Bank A Read from Bank A
W
Random Column Read ac waveforms
BA0
BA1
A10
Address
LDQM/ UDQM
Low
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
DQ0-DQ15
Hi-Z
Bank/Row Activate in Bank A
M65KA512AB
AI09955
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
KE
E
RAS
CAS
1. Burst Length = 8 words, Latency = 3 clock cycles.
RBa RAa RBb RBa CBa RAa CAa RBb CBb QBa1 QBa2 QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 Read from Bank B Bank/Row Activate in Bank A Read from Bank A Precharge in Bank B Bank/Row Activate in Bank B Read from Bank A
W
Figure 10. Random Row Read ac waveforms
BA0
BA1
A10
Address
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
QAa2 QAa3 QAa4 QAa5 QAa6 QAa7
Bank/Row Activate in Bank B
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from row m in Bank A.
DC and ac parameters
AI09957
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36/55
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T0
DC and ac parameters
K
High
KE
E
RAS
CAS
1. Burst Length = 4 words, Latency = 3 clock cycles.
RAa RDa RAa RDa CDa CAa CDb CDc CAb QAa1 DQN QAa2 QAa3 QAa4 QDa1 QDa2 QDb1 QDb2 QDc1 QDc2 QAb1 QAb2 QAb3 QAb4 Read from Bank A Bank/Row Activate in Bank D Read from Bank D Read from Bank D Read from Bank D Read from Bank A Precharge in Bank D Precharge in Bank A
W
BA0
Figure 11. Column Interleaved Read ac waveforms
BA1
A10
Address
LDQM/ UDQM
Low
Hi-Z
DQ0-DQ15
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAmn= Data n read from Column m in Bank A.
Bank/Row Activate in Bank A
M65KA512AB
AI09520
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
KE
E
RAS
CAS
1. Burst Length = 4 words, Latency = 3 clock cycles.
RAa RDa RDb RAa RDa CDa CAa CAb RDb CDb
DQN
W
BA0
BA1
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
Read from Bank A Bank/Row Activate in Bank D Read + Auto Precharge from Bank D Read + Auto Precharge from Bank A Auto Precharge from Bank D Bank/Row Activate in Bank D Read + Auto Precharge from Bank D Autoprecharge Start from Bank A
A10
Address
LDQM/ UDQM
Low
Hi-Z
Figure 12. Burst Column Read followed by Auto Precharge ac waveforms
DQ0-DQ15
Bank/Row Activate in Bank A
DC and ac parameters
37/55
AI09961b
38/55
T0 K tCKS KE tCH, tAH E tCS, tAS RAS tCKH T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 CAS W BA0 BA1 A10 Address LDQM/ UDQM Low tDH DQ0-DQ15 tDS tRCD tRRD tRC tRCD tRAS tRC Bank/Row Activate in Bank C Bank/Row Activate in Bank B Write to Bank B Auto Precharge Start from Bank C Precharge in Bank B Bank/Row Activate in Bank C Bank/Row Activate in Bank B Hi-Z
DQN
1. Burst Length = 4 words.
tDAL tDPL tRP Write + Auto Precharge to Bank C
AI09947
DC and ac parameters M65KA512AB
Figure 13. Write ac waveforms
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
M65KA512AB
High
KE
1. Burst Length = 4 words.
Lower Byte Read Upper Byte Read Upper Byte Write Upper Byte Read Upper Byte Read
AI09963b
E
RAS
CAS
Figure 14. Byte Write ac waveforms
W
BA0
BA1
A10
Address
LDQM
UDQM
DQ0-DQ7
Hi-Z
DQ8-DQ15
Hi-Z
DC and ac parameters
Bank/Row Activate Read in Bank D from Bank D
Lower Byte Read from Write Bank D Upper Byte Write
39/55
DC and ac parameters Figure 15. Mode Register Set ac waveforms
T0 K High KE tMRD, 2 Clock Cycles (min) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
M65KA512AB
T12
T13
E
RAS
CAS
W
BA0
BA1
A10
Address
MR
Data (2)
LDQM/ UDQM
DQ0-DQ15
Hi-Z tRP Precharge All Banks Mode Register Set Bank/Row Activate Valid
AI09948
1. To program the Extended Mode Register, BA0 and BA1 must be set to `0' and `1' respectively, and A0 to A11 to the Extended Mode Register Data. 2. MR Data is the value to be written to the Mode Register.
40/55
M65KA512AB
T0 K
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
KE
E
RAS
CAS
W
BA0
BA1
Figure 16. Clock Suspend during Burst Write ac waveforms
A10
RAa
Address RAa CAa
LDQM/ UDQM Low Hi-Z DQ0-DQ15
1. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAan= Data n Written to Column a in Bank A.
DAa1 DAa2 DAa3 DAa4 Bank/Row Activate in Bank A Write to Bank A Clock Suspended during 1 cycle Clock Suspended during 2 cycles Clock Suspended during 3 cycles
DC and ac parameters
41/55
AI09950b
42/55
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
DC and ac parameters
K
High
1. Burst Length = 4 words.
RDa RDd RDa CDa CDb CDc RDd CDd DDa1 DDa2 DDa3 DDa4 DQN DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 Write to Bank D Write to Bank D Write to Bank D Precharge in Bank D Bank/Row Activate in Bank D Write to Bank D
KE
E
RAS
CAS
W
Figure 17. Random Column Write ac waveforms
BA0
BA1
A10
Address
LDQM/ UDQM
Low
2. RDa = Address of Row a in Bank D, CDa = Address of Column a in Bank D, DDmn= Data n written to Column m in Bank D.
DQ0-DQ15
Hi-Z
DDd2
Bank/Row Activate in Bank D
M65KA512AB
AI09956
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
1. Burst Length = 8 words.
RAa RDa RAb RAa CAa RDa CDa RAb CAb DAa1 DAa2 DAa3 DAa4 DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1 DAb2 Write to Bank A Bank/Row Activate in Bank D Write to Bank D Precharge in Bank A Bank/Row Activate in Bank A Write to Bank A
KE
E
RAS
CAS
W
Figure 18. Random Row Write ac waveforms
BA0
BA1
A10
Address
LDQM/ UDQM
Low
DQ0-DQ15
Hi-Z
Bank/Row Activate in Bank A
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to row m in Bank A.
DC and ac parameters
AI09958
43/55
44/55
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T0
DC and ac parameters
K
High
KE
1. Burst Length = 4 words.
RBa CAa RBa CBa CBb CBc CAb CBd
DQN DAa1
E
RAS
CAS
W
BA0
Figure 19. Column Interleaved Write ac waveforms
BA1
A10
RAa
Address
RAa
LDQM/ UDQM DAa2 DAa3 DAa4 DBa1
Low
Hi-Z
DQ0-DQ15
DBa2
DBb1
DBb2
DBc1
DBc2
DAb1
DAb2
DBb1
DBb2 DBb3
DBb4
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, DAmn= Data n written to Column m in Bank A.
Write to Bank A Bank/Row Activate in Bank B Write to Bank B Write to Bank B Write to Bank B Write to Bank A Write to Bank B Precharge in Bank A Precharge in Bank B
AI09521
M65KA512AB
Bank/Row Activate in Bank A
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K
High
1. Burst Length = 4 words
RAa RDa RDb RAa RDa CDa CAa CAb RDb CDb
DQN
KE
E
RAS
CAS
W
BA0
BA1
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A.
Bank/Row Activate in Bank D Write to Bank A Write + Auto Precharge from Bank D Write + Auto Precharge from Bank A Auto Precharge Start from Bank D Bank/Row Write + Activate Auto Precharge in Bank D from Bank D Auto Precharge Start from Bank A
A10
Address
LDQM/ UDQM
Low
Figure 20. Burst Column Write followed by Auto Precharge ac waveforms
DQ0-DQ15
Hi-Z
Bank/Row Activate in Bank A
DC and ac parameters
45/55
AI09962
46/55
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
T0
DC and ac parameters
K
High
KE
E
RAS
CAS
1. Burst Length = 8 words, Latency = 3 clock cycles.
RAa RAb RAc RAa Write Masking CAa RAb CAb RAc DAa1 tRCD tRAS Write to Bank A Precharge in Bank A + Write Terminated Bank/Row Activate in Bank A tDPL DAa2 DAa3 DQDAa4 N DAa5 tRP tRAS Read from Bank A Precharge in Bank A + Read Terminated QAb1 QAb2 QAb3 DQQAb4 N
W
BA0
Figure 21. Precharge termination ac waveforms
BA1
A10
Address
LDWM/ UDQM
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A, DAan= Data n written to Column a in Bank A.
DQ0-DQ15
Hi-Z
Bank/Row Activate in Bank A
Bank/Row Activate in Bank A
AI09524
M65KA512AB
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
K 1 Clock Cycle needed High Level nedeed tMRD tMRD 2 Refresh Cycles needed
KE
E
RAS
CAS
W
Figure 22. Power-On sequence ac waveforms
BA0
BA1
A10
Address
MR Data (1)
EMR Data (1)
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z tRP tRC1 CBR Auto Refresh tRC1 Bank/Row Activate
AI09960b
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Precharge All Banks Mode Extended Mode CBR Register Set Register Set Auto Refresh
DC and ac parameters
47/55
48/55
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 tCKSP tCKSP RAa RAa CAa Low Hi-Z QAa1 QAa2 QAa3 QAa4 Bank/Row Activate in Bank A Power-Down Entry Read from Bank A Start of Clock Masking End of Clock Masking Precharge in Bank A
K
DC and ac parameters
KE
E
RAS
1. Burst Length = 4 words, Latency = 3 clock cycles.
Power-Down Exit Power-Down Entry Power-Down Exit ACTIVE STANDBY PRECHARGE STANDBY
AI09951
CAS
W
BA0
BA1
Figure 23. Power-Down mode and Clock Masking ac waveforms
A10
Address
LDQM/ UDQM
2. RAa = Address of Row a in Bank A, CAa = Address of Column a in Bank A, QAan= Data n read from Column a in Bank A.
DQ0-DQ15
M65KA512AB
M65KA512AB
T0
T1
T2
T3
T4
T5
T6
Tn
Tn+1
Tn+2
Tn+3
Tn+4
Tn+5
Tn+6
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6
Tm+7
K High
KE
E
RAS
CAS
Figure 24. Auto refresh ac waveforms
W
BA0
BA1
A10
Address
LDQM/ UDQM Low Hi-Z tRP Precharge (optional) Auto Refresh
DQ0-DQ15
tRC1 Auto Refresh
tRC1 Bank/Row Activate Read
AI09952c
DC and ac parameters
49/55
50/55
T0 T1 T2 T3 T4 Tn Tn+1 Tn+2 Tm Tm+1 Tk Tk+1 Tk+2 Tk+3 Tk+4
DC and ac parameters
K
KE
E
RAS
CAS
Figure 25. Self refresh ac waveforms
W
BA0
BA1
A10
Address
LDQM/ UDQM Low Hi-Z tRP
DQ0-DQ15
tRC2
tRC2
Precharge (optional)
Self Refresh Entry
Self Refresh Exit
Self Refresh Exit
Bank/Row Activate
M65KA512AB
Self Refresh Entry (or Bank/Row Activate) Next Clock Enable
Next Clock Enable
AI09953b
M65KA512AB Figure 26. Deep Power-Down Entry ac waveforms
T0 K T1 T2 T3 T4
DC and ac parameters
T5
KE
E
RAS
CAS
W
A10
DQ0-DQ15
Hi-Z tRP Precharge All Banks (optional) Deep Power-Down Entry
ai07720c
1. BA0, BA1 and address bits A0 to A12 are `Don't Care'.
51/55
1
52/55
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 1 Clock Cycle needed High Level nedeed tMRD tMRD 2 Refresh Cycles needed
DC and ac parameters
K
KE
E
RAS
CAS
W
Figure 27. Deep Power-Down Exit ac waveforms
BA0
BA1
A10
Address
MR Data (1)
EMR Data (1)
High
LDQM/ UDQM
DQ0-DQ15 Hi-Z 200s tRP tRC1 Auto Refresh tRC1 Bank/Row Activate
AI09954c
1. MR Data and EMR data are the values to be written to the Mode Register and the Extended Mode Register, respectively.
Precharge All Banks Mode Extended Mode Auto Refresh Register Set Register Set
M65KA512AB
Deep Power-Down Exit
M65KA512AB
Part numbering
8
Part numbering
Table 14.
Example:
Ordering information scheme
M65KA512A B8 W3
Device type M65 = Low- Power SDRAM
Architecture K = Bare Die
Operating voltage A = VDD = VDDQ = 1.8V, Standard LPSDRAM, x16
Array organization 512 = 4 Banks x 8 Mbit x 16
Option 1 A = One Chip Enable
Option 2 B = B Die
Speed 8 = 7.5ns
Package W = Unsawn wafer
Temperature range 8 = -30 to 85 C
For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
53/55
Revision history
M65KA512AB
9
Revision history
Date 18-Nov-2005 Revision 0.1 Initial release. Table 8: Capacitance and Table 11: Self-Refresh current values in Normal Operating Mode filled-in. Table 10: DC characteristics 2 and Table 12: AC characteristics 1 updated. Wafer and Die specifications section removed. Changed Burst Stop to Burst Terminate in Features; changed the Operating Temperature Range from - 25 to - 30 in Features, Table 6, Table 7, Table 9, Table 10, Table 11, and Table 14; updated footnotes in Table 7, Table 9, Table 10, and Table 12; updated tT value in Table 7: Operating and ac measurement conditions; updated package information and removed option `T' in Table 14: Ordering information scheme. tRCD minimum value updated in Table 13: AC characteristics 2. Changes
31-Jan-2006
1.0
12-Sep-2006
2
20-Mar-2007
3
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M65KA512AB
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